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RoboClock(R), CY7B9950
2.5/3.3V, 200 MHz High-Speed Multi-Phase PLL Clock Buffer
Features

Description
The CY7B9950 RoboClock(R) is a low voltage, low power, eight-output, 200 MHz clock driver. It features output phase programmability which is necessary to optimize the timing of high performance computer and communication systems. The user can program the phase of the output banks through nF[0:1] pins. The adjustable phase feature allows the user to skew the outputs to lead or lag the reference clock. Any one of the outputs can be connected to the feedback input to achieve different reference frequency multiplications, and divide ratios and zero input-output delay. The device also features split output bank power supplies, which enable the user to run two banks (1Qn and 2Qn) at a power supply level different from that of the other two banks (3Qn and 4Qn). Additionally, the three-level PE/HD pin controls the synchronization of the output signals to either the rising, or the falling edge of the reference clock and selects the drive strength of the output buffers. The high drive option (PE/HD = MID) increases the output current from 12 mA to 24 mA(3.3V).
2.5V or 3.3V operation Split output bank power supplies Output frequency range: 6 MHz to 200 MHz 50 ps typical matched-pair Output-output skew 50 ps typical Cycle-cycle jitter 49.5/50.5% typical output duty cycle Selectable output drive strength Selectable positive or negative edge synchronization Eight LVTTL outputs driving 50 terminated lines LVCMOS/LVTTL over-voltage-tolerant reference input Phase adjustments in 625-/1250-ps steps up to +7.5 ns 2x, 4x multiply and (1/2)x, (1/4)x divide ratios Spread-Spectrum compatible Industrial temp. range: -40C to +85C 32-pin TQFP package
Logic Block Diagram
TEST PE/HD FS VDDQ1
REF FB
3
3
3
PLL
3
1F1:0
3
Phase Select
1Q0 1Q1
3
2F1:0
3
Phase Select
2Q0 2Q1
3
3F1:0
3
Phase Select and /K
3Q0 3Q1 VDDQ3
3
4F1:0
3
Phase Select and /M
4Q0 4Q1
VDDQ4 sOE#
Cypress Semiconductor Corporation Document #: 38-07338 Rev. *D
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised September 27, 2007
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CY7B9950
Pinouts
Figure 1. Pin Diagram - 32 Pin TQFP package Top view
TEST VDD REF VSS 3F0 2F1 26 2F0 25 24 23 22 1F1 1F0 sOE# VDDQ1 1Q0 1Q1 VSS VSS 21 20 19 18 17 10 11 12 13 14 VDD 15 2Q1 VDDQ3 2Q0 16 9
32
31
FS
30
29
28 FB
3F1 4F0 4F1 PE/HD VDDQ4 4Q1 4Q0 VSS
1 2 3 4 5 6 7 8
CY7B9950
3Q1
Document #: 38-07338 Rev. *D
VSS
3Q0
27
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Table 1. Pin Definitions Pin 29 13 27 Name REF FB TEST IO[1] I I I Type LVTTL/LVCMOS Reference Clock Input. LVTTL Three-level Feedback Input. When MID or HIGH, disables Phase-locked Loop (PLL)[3]. REF goes to outputs of Bank 1 and Bank 2. REF also goes to outputs of Bank 3 and Bank 4 through output dividers K and M. Set LOW for normal operation. Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q0 and 2Q1) in a LOW state (for PE = H or M) - 2Q0, and 2Q1 may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and sOE# is HIGH, the nF[1:0] pins act as output disable controls for individual banks when nF[1:0] = LL. Set sOE# LOW for normal operation. Selects Positive or Negative Edge Control and High or Low Output Drive Strength. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference clock, respectively. When at MID level, the output drive strength is increased and the outputs synchronize with the positive edge of the reference clock (see Table 7 on page 4). Select Frequency and Phase of the Outputs (see Table 2, Table 3, Table 4 on page 4, Table 5 on page 4, and Table 6 on page 4). Selects VCO Operating Frequency Range (see Table 5 on page 4) Four Banks of Two Outputs (see Table 2, Table 3, and Table 4 on page 4) Description
22
sOE#
I, PD
Two-level
4
PE/HD
I, PU
Three-level
24, 23, 26, 25, 1, 32, 3, 2 31
nF[1:0]
I
Three-level
FS
I O
Three-level LVTTL
19, 20, 15, nQ[1:0] 16, 10, 11, 6, 7 21 12 5 14,30 8,9,17,18,28
VDDQ1[2] PWR VDDQ3[2] PWR VDDQ4[2] PWR VDD[2] VSS PWR PWR
Power Power Power Power Power
Power Supply for Bank 1 and Bank 2 Output Buffers (see Table 8 on page 4 for supply level constraints). Power Supply for Bank 3 Output Buffers (see Table 8 on page 4 for supply level constraints). Power Supply for Bank 4 Output Buffers (see Table 8 on page 4 for supply level constraints). Power Supply for Internal Circuitry (see Table 8 on page 4 for supply level constraints). Ground Table 3. Output Divider Settings -- Bank 4 4F[1:0] LL Other[4] M -- Bank4 Output Divider 2 1
Device Configuration
The outputs of the CY7B9950 can be configured to run at frequencies ranging from 6 to 200 MHz. Banks 3 and 4 output dividers are controlled by 3F[1:0] and 4F[1:0] as indicated in Table 2 and Table 3, respectively. Table 2. Output Divider Settings -- Bank 3 3F[1:0] LL HH Other[4] K -- Bank3 Output Divider 2 4 1
The three-level FS control pin setting determines the nominal operating frequency range of the divide-by-one outputs of the device. The CY7B9950 PLL operating frequency range that corresponds to each FS level is given in Table 4 on page 4.
Notes 1. "PD" indicates an internal pull-down and "PU" indicates an internal pull-up. "3" indicates a three-level input buffer 2. A bypass capacitor (0.1F) must be placed as close as possible to each positive power pin (< 0.2"). If these bypass capacitors are not close to the pins their high-frequency filtering characteristic are cancelled by the lead inductance of the traces. 3. When TEST = MID and sOE# = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain in effect unless nF[1:0] = LL. 4. These states are used to program the phase of the respective banks (see Table 6 on page 4).
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Table 4. Frequency Range Select FS L M H PLL Frequency Range 24 to 50 MHz 48 to 100 MHz 96 to 200 MHz
the tU value is: tU = 1 / (fNOM x MF), where MF is a multiplication factor, which is determined by the FS setting as indicated in Table 5. Table 5. MF Calculation FS L M H MF 32 16 8 fNOM at which tU is 1.0 ns(MHz) 31.25 62.5 125
The selectable output skew is in discrete increments of time units (tU).The value of tU is determined by the FS setting and the maximum nominal frequency. The equation used to determine Table 6. Output Skew Settings nF[1:0] LL[5] LM LH ML MM MH HL HM HH Skew (1Q[0:1],2Q[0:1]) -4tU -3tU -2tU -1tU Zero Skew +1tU +2tU +3tU +4tU
Skew (3Q[0:1]) Divide By 2 -6tU -4tU -2tU Zero Skew +2tU +4tU +6tU Divide By 4
Skew (4Q[0:1]) Divide By 2 v6tU -4tU v2tU Zero Skew +2tU +4tU +6tU Inverted[6]
In addition to determining whether the outputs synchronize to the rising or the falling edge of the reference signal, the 3-level PE/HD pin controls the output buffer drive strength as indicated in Table 7. The CY7B9950 features split power supply buses for Banks 1 and 2, Bank 3 and Bank 4, which enables the user to obtain both 3.3V and 2.5V output signals from one device. The core power supply (VDD) must be set a level that is equal or higher than on any one of the output power supplies. Table 7. PE/HD Settings PE/HD L M H Synchronization Negative Positive Positive Output Drive Strength[7] Low Drive High Drive Low Drive
Governing Agencies
The following agencies provide specifications that apply to the CY7B9950. The agency name and relevant specification is listed below. Table 9. Governing Agencies and Specifications Agency Name JEDEC IEEE UL-194_V0 MIL Specification JESD 51 (Theta JA) JESD 65 (Skew, Jitter) 1596.3 (Jitter Specs) 94 (Moisture Grading) 883E Method 1012.1 (Therma Theta JC)
Table 8. Power Supply Constraints VDD 3.3V 2.5V VDDQ1[8] 3.3V or 2.5V 2.5V VDDQ3[8] 3.3V or 2.5V 2.5V VDDQ4[8] 3.3V or 2.5V 2.5V
Notes: 5. LL disables outputs if TEST = MID and sOE# = HIGH. 6. When 4Q[0:1] are set to run inverted (HH mode), sOE# disables these outputs HIGH when PE/HD = HIGH or MID and sOE# disables them LOW when PE/HD = LOW. 7. Please refer to "DC Parameters" section for IOH/IOL specifications. 8. VDDQ1/3/4 must not be set at a level higher than that of VDD. They can be set at different levels from each other, e.g., VDD = 3.3V, VDDQ1 = 3.3V, VDDQ3 = 2.5V and VDDQ4 = 2.5V.
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Absolute Maximum Conditions
Parameter VDD VDD VIN(MIN) VIN(MAX) TS TA TJ OJC OJA ESDHBM UL-94 MSL FIT Description Operating Voltage Operating Voltage Input Voltage Input Voltage Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient Flammability Rating Moisture Sensitivity Level Failure in Time Manufacturing Testing Condition Functional @ 2.5V 5% Functional @ 3.3V 10% Relative to VSS Relative to VDD Non-functional Functional Functional Mil-Spec 883E Method 1012.1 JEDEC (JESD 51) At 1/8 in. Min 2.375 2.97 VSS - 0.3 - -65 -40 - - - 2000 V-0 1 10 ppm Max 2.625 3.63 - VDD + 0.3 +150 +85 155 42 105 - Unit V V V V C C C C/W C/W V
ESD Protection (Human Body Model) MIL-STD-883, Method 3015
DC Electrical Specifications at 2.5V
Parameter VDD VIL VIH VIHH
[9]
Description 2.5 Operating Voltage Input LOW Voltage Input HIGH Voltage Input HIGH Voltage Input MID Voltage Input LOW Voltage Input Leakage Current 3-Level Input DC Current 2.5V 5%
Condition REF, FB and sOE# Inputs
Min 2.375 - 1.7
Max 2.625 0.7 -
Unit V V V V V V A A A A A A V V V V mA mA pF
VIMM[9] VILL[9] IIL I3
3-Level Inputs - VDD - 0.4 (TEST, FS, nF[1:0], PE/HD) (These pins V /2 - 0.2 V /2 + 0.2 DD are normally wired to VDD, GND or uncon- DD - 0.4 nected.) VIN = VDD/GND, VDD = max. (REF and FB inputs) HIGH, VIN = VDD MID, VIN = VDD/2 LOW, VIN = VSS 3-Level Inputs (TEST, FS, nF[1:0], DS[1:0], PD#/DIV, PE/HD) -5 - -50 -200 -25 - - - 2.0 2.0 - 150 4 5 200 50 - - 100 0.4 0.4 - - 2
IPU IPD VOL VOH IDDQ IDD CIN
Input Pull-up Current Input Pull-down Current Output LOW Voltage Output HIGH Voltage
VIN = VSS, VDD = max. VIN = VDD, VDD = max., (sOE#) IOL = 12 mA (PE/HD = L/H), (nQ[0:1]) IOL = 20 mA (PE/HD = MID), (nQ[0:1]) IOH = -12 mA (PE/HD = L/H), (nQ[0:1]) IOH = -20 mA (PE/HD = MID), (nQ[0:1]) VDD = max., TEST = MID, REF = LOW, sOE# = LOW, outputs not loaded At 100 MHz
Quiescent Supply Current Dynamic Supply Current Input Pin Capacitance
Note 9. These inputs are normally wired to VDD, GND or unconnected. Internal termination resistors bias unconnected inputs to VDD/2.
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DC Specifications at 3.3V
Parameter VDD VIL VIH VIHH[9] VIMM[9] VILL[9] IIL I3 Description 3.3 Operating Voltage Input LOW Voltage Input HIGH Voltage Input HIGH Voltage Input MID Voltage Input LOW Voltage Input Leakage Current 3-Level Input DC Current 3-Level Inputs (TEST, FS, nF[1:0], PE/HD) (These pins are normally wired to VDD,GND or unconected.) VIN = VDD/GND,VDD = max. (REF and FB inputs) HIGH, VIN = VDD MID, VIN = VDD/2 LOW, VIN = VSS IPU IPD VOL VOH IDDQ IDD CIN Input Pull-up Current Input Pull-down Current Output LOW Voltage Output HIGH Voltage 3-Level Inputs (TEST, FS, nF[1:0], DS[1:0], PD#/DIV, PE/HD) 3.3V 10% REF, FB and sOE# Inputs Condition Min 2.97 - 2.0 VDD - 0.6 VDD/2 - 0.3 - -5 - -50 -200 -100 - - - 2.4 2.4 - 230 4 Max 3.63 0.8 - - VDD/2 + 0.3 0.6 5 200 50 - - 100 0.4 0.4 - - 2 Unit V V V V V V A A A A A A V V V V mA mA pF
VIN = VSS, VDD = max. VIN = VDD, VDD = max., (sOE#) IOL = 12 mA (PE/HD = L/H), (nQ[0:1]) IOL = 24 mA (PE/HD = MID), (nQ[0:1]) IOH = -12 mA (PE/HD = L/H), (nQ[0:1]) IOH = -24 mA (PE/HD = MID), (nQ[0:1]) VDD = max., TEST = MID, REF = LOW, sOE# = LOW, outputs not loaded At 100 MHz
Quiescent Supply Current Dynamic Supply Current Input Pin Capacitance
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AC Test Loads and Waveforms
Figure 2. AC Test Loads
VDDQ
Output 20 pF Output
150
150
20 pF
For Lock Output
For All Other Outputs
Figure 3. Output Waveforms
tORISE tOFALL tORISE tOFALL
2.0V VTH =1.5V tPW L 0.8V
tPWH
1.7V VTH =1.25V 0.7V
tPWH
tPWL
3.3V LVTTL OUTPUT WAVEFORM
2.5V LVTTL OUTPUT WAVEFORM
Figure 4. Test Waveforms
1 ns
3.0V 2.0V VTH =1.5V 0.8V 0V
1 ns
2.5V 1.7V VTH =1.25V 0.7V 0V
1 ns
1 ns
3.3V LVTTL INPUT TEST WAVEFORM
2.5V LVTTL INPUT TEST WAVEFORM
AC Input Specifications
Parameter
TR,TF TPWC TDCIN FREF
Description
Input Rise/Fall Time Input Clock Pulse Input Duty Cycle Reference Input Frequency FS = LOW FS = MID FS = HIGH 0.8V - 2.0V HIGH or LOW
Condition
Min
- 2 10 6 12 24
Max
10 - 90 50 100 200
Unit
ns/V ns % MHz
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Switching Characteristics
Parameter FOR VCOLR VCOLBW tSKEWPR tSKEW0 tSKEW1 tSKEW2 tSKEW3 tSKEW4 tSKEW5 tPART tPD0 tODCV Part-Part Skew Output-Output Skew[10] Description Output Frequency Range VCO Lock Range VCO Loop Bandwidth Matched-Pair Skew[10] Output-Output Skew[10] Skew between the earliest and the latest output transitions within the same bank. Skew between the earliest and the latest output transitions among all outputs at 0tU. Skew between the earliest and the latest output transitions among all outputs for which the same phase delay has been selected. Skew between the nominal output rising edge to the inverted output falling edge. Skew between non-inverted outputs running at different frequencies. Skew between nominal to inverted outputs running at different frequencies. Skew between nominal outputs at different power supply levels. Skew between the outputs of any two devices under identical settings and conditions (VDDQ,VDD,temp, air flow, frequency, etc.). Condition Min 6 200 0.25 - - - Typ - - - 50 100 100 Max 200 400 3.5 100 200 200 Unit MHz MHz MHz ps ps ps
- - - - -
- - - - -
500 500 500 650 750
ps ps ps ps ps
Ref-FB Propagation Delay[11] Output Duty Cycle Fout < 100 MHz, measured at VDD/2 Fout > 100 MHz, measured at VDD/2
-250 48 45 - - 0.15 - Divide by one output frequency, FS = L, FB = divide by 1, 2, 4. Divide by one output frequency, FS = M/H, FB = divide by 1, 2, 4. - -
- 49.5/ 50.5 48/ 52 - - - - 50 70
+250 52 55 1.5 2.0 1.5 0.5 100 150
ps %
tPWH tPWL tR/tF tLOCK tCCJ
Output High Time Deviation from 50% Output Low Time Deviation from 50% Output Rise/Fall Time PLL lock time[12,13] Cycle-Cycle Jitter
Measured at 2.0V for VDD = 3.3V and at 1.7V for VDD = 2.5V. Measured at 0.8V for VDD = 3.3V and at 0.7V for VDD = 2.5V. Measured at 0.8V - 2.0V for VDD = 3.3V and 0.7V-1.7V for VDD = 2.5V.
ns ns ns ms ps ps
Note 10. Test load = 20 pF, terminated to VCC/2. All outputs are equally loaded. 11. tPD is measured at 1.5V for VDD = 3.3V and at 1.25V for VDD = 2.5V with REF rise/fall times of 0.5 ns between 0.8V - 2.0V. 12. tLOCK is the time that is required before outputs synchronize to REF. This specification is valid with stable power supplies which are within normal operating limits. 13. Lock detector circuit may be unreliable for input frequencies lower than 4 MHz, or for input signals which contain significant jitter.
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AC Timing Definitions
Figure 5. Timing Definitions
tREF tPW H tPW L
REF
tPD t0DCV t0DCV
FB
tCCJ1-12
Q
tSKEW PR tSKEW 0,1
tSKEW PR tSKEW 0,1
OTHER Q
tSKEW 1
tSKEW 1
INVERTED Q
tSKEW3
tSKEW 3
tSKEW3
REF DIVIDED BY 2
tSKEW1,3,4
tSKEW 1,3,4
REF DIVIDED BY 4
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Ordering Information
Part Number CY7B9950AC CY7B9950ACT CY7B9950AI CY7B9950AIT Pb-free CY7B9950AXC CY7B9950V-5AXC CY7B9950AXCT CY7B9950AXI CY7B9950AXIT 32 TQFP 32 TQFP 32 TQFP - Tape and Reel 32 TQFP 32 TQFP - Tape and Reel Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Industrial, -40 to 85C Industrial, -40 to 85C Active Active Active Active Active 32 TQFP 32 TQFP - Tape and Reel 32 TQFP 32 TQFP - Tape and Reel Package Type Product Flow Commercial, 0 to 70C Commercial, 0 to 70C Industrial, -40 to 85C Industrial, -40 to 85C Status Not for new design Not for new design Not for new design Not for new design
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Package Drawing and Dimension
Figure 6. 32-lead Thin Plastic Quad Flatpack 7 x 7 x 1.0 mm A32
51-85063-*B
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Document History Page
Document Title: RoboClock(R) CY7B9950 2.5/3.3V, 200 MHz High-Speed Multi-Phase PLL Clock Buffer Document Number: 38-07338 Rev. ** *A *B ECN No. 121663 122548 124646 Issue Date 11/25/02 12/12/02 03/05/03 Orig. of Change RGL RGL RGL New Data Sheet Removed the PD#/DIV and DS[1:0] pins in VIHH,VIMM and VILL for both 2.5V and 3.3V DC Electrical Specs tables Corrected the description of Pin 27(TEST) in the Pin Description table Corrected the description of Pin 12 (VDDQ) in the Pin Description table Corrected the Min and Max values of VDD from 2.25/2.75 to 2.375/2.625 Volts in the Absolute Maximum Conditions table Added Lead-free devices Added Jitter typical values Description of Change
*C *D
433662 1562063
See ECN See ECN
RGL
PYG/AESA Added Lead-free CY7B9940V-5AXC to Ordering Information Added Status column to Ordering Information table
(c) Cypress Semiconductor Corporation, 2002-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-07338 Rev. *D
Revised September 27, 2007
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RoboClock is a registered trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. All products and company names mentioned in this document may be the trademarks of their respective holders.
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